This section introduces aspects that may facilitate a better understanding of the disclosure. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is in the prior art or what is not in the prior art.
VICs are widely used to build lumped-element based components in multilayered low-temperature co-fired ceramic (LTCC) substrates, as shown in FIG. 1. However, a VIC, as a dual port device, shows a number of additional undesired resonant frequencies that limit its operational bandwidth. Particularly, spurious spikes in |S11|, which is defined as an input reflection coefficient of a dual port device with its output port being terminated by a matched load, and in |S21|, which is defined as a forward transmission insertion loss of the dual port device with its output port being terminated by a matched load can be observed at several frequencies. These frequencies where the spurious spikes occur limit the bandwidth of the VIC. Moreover, an increase in the number of fingers (which will interchangeably be referred to as metal plates hereafter) may result in more undesired resonances at lower frequencies, which may further limit the bandwidth of the VIC.
For a planar interdigital capacitor, spurious spikes can be reduced by using inductive parts as recited in reference document [1], bond wires as recited in reference document [2] or a slotted ground structure with via holes as recited in reference document [3] between interval fingers of the planar interdigital capacitor. However there is not any effective approach for removing or reducing spurious spikes of a vertically-interditigal-capacitor for bandwidth enhancement.